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FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
Integrated Device Technology, Inc.
IDT54/74FCT273T/AT/CT
FEATURES:
* * * * Std., A, and C speed grades Low input and output leakage 1A (max.) CMOS power levels True TTL input and output compatibility - VOH = 3.3V (typ.) - VOL = 0.3V (typ.) High drive outputs (-15mA IOH, 48mA IOL) Meets or exceeds JEDEC standard 18 specifications Product available in Radiation Tolerant and Radiation Enhanced versions Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) Available in DIP, SOIC, QSOP, CERPACK and LCC packages
DESCRIPTION:
The IDT54/74FCT273T/AT/CT are octal D flip-flops built using an advanced dual metal CMOS technology. The IDT54/ 74FCT273T/AT/CT have eight edge-triggered D-type flipflops with individual D inputs and O outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's O output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.
* * * * *
MR
FUNCTIONAL BLOCK DIAGRAM
D0 CP D CP RD MR O0 O1 O2 O3 O4 O5 O6 O7
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D1
D2
D3
D4
D5
D6
D7
Q
D CP RD
Q
D CP RD
Q
D CP RD
Q
D CP RD
Q
D CP RD
Q
D CP RD
Q
D CP RD
Q
PIN CONFIGURATIONS
D0
3 D1 O1 O2 D2 D3 4 5 6 7 8 9 10 11 12 13
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MR O0 D0 D1 O1 O2 D2 D3 O3 GND
2 3 4 5 6 7 8 9 10
19 P20-1 D20-1 SO20-2 SO20-8 & E20-1 18 17 16 15 14 13 12 11
O7 D7 D6 O6 O5 D5 D4 O4 CP
2 1 20 19 18 17 L20-2 16 15 14 D7 D6 O6 O5 D5
O0
1
20
VCC
O3 GND
CP O4 D4
MR VCC O7
INDEX
2568 drw 02
DIP/SOIC/QSOP/CERPACK TOP VIEW
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
LCC TOP VIEW
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(c)1995 Integrated Device Technology, Inc.
APRIL 1995
DSC-4209/3
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IDT54/74FCT273T/AT/CT FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Pin Names DN
MR
FUNCTION TABLE(1)
Description Operating Mode Reset (Clear) Load "1" Load "0"
2568 tbl 01
MR
Data Inputs Master Reset (Active LOW) Clock Pulse Input (Active Rising Edge) Data Outputs
Inputs CP X
DN X h I
Outputs ON L H L
L H H
CP ON
NOTE: 2568 tbl 02 1. H = HIGH voltage level steady state h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition L = LOW voltage level steady state I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition X = Don't Care = LOW-to-HIGH Clock Transition
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Rating Commercial VTERM(2) Terminal Voltage -0.5 to +7.0 with Respect to GND VTERM(3) Terminal Voltage -0.5 to with Respect to VCC +0.5 GND TA Operating 0 to +70 Temperature TBIAS Temperature -55 to +125 Under Bias TSTG Storage -55 to +125 Temperature PT Power Dissipation 0.5 IOUT DC Output Current -60 to +120 Military -0.5 to +7.0 Unit V
CAPACITANCE (TA = +25C, f = 1.0MHz)
Symbol Parameter(1) CIN Input Capacitance COUT Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 6 8 Max. Unit 10 pF 12
pF
2568 lnk 04
-0.5 to VCC +0.5 -55 to +125 -65 to +135 -65 to +150 0.5 -60 to +120
V C C C W mA
NOTE: 1. This parameter is measured at characterization but not tested.
2568 lnk 03 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed VCC by +0.5V unless otherwise noted. 2. Input and VCC terminals only. 3. Outputs and I/O terminals only.
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IDT54/74FCT273T/AT/CT FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0C to +70C, VCC = 5.0V 5%; Military: TA = -55C to +125C, VCC = 5.0V 10%
Symbol VIH VIL II H II L II VIK IOS VOH Parameter Input HIGH Level Input LOW Level Input HIGH Current (4) Input LOW Current (4) Input HIGH Current (4) Clamp Diode Voltage Short Circuit Current Output HIGH Voltage Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VCC = Max. VCC = Min., IN = -18mA VCC = Max.(3) , VO = GND VCC = Min. VIN = VIH or VIL IOH = -6mA MIL. IOH = -8mA COM'L. IOH = -12mA MIL. IOH = -15mA COM'L. IOL = 32mA MIL. IOL = 48mA COM'L.
--
Min. 2.0 -- -- -- -- -- -60 2.4 2.0 -- -- --
Typ.(2) -- -- -- -- -- -0.7 -120 3.3 3.0 0.3 200 0.01
Max. -- 0.8 1 1 1 -1.2 -225 -- -- 0.5 -- 1
Unit V V A A A V mA V V V mV mA
2568 tbl 05
VI = 2.7V VI = 0.5V
VCC = Max., VI = VCC (Max.)
VOL VH ICC
Output LOW Voltage Input Hysteresis Quiescent Power Supply Current
VCC = Min. VIN = VIH or VIL VCC = Max. VIN = GND or VCC
NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second. 4. The test parameter for this parameter is 5A at TA = -55C.
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IDT54/74FCT273T/AT/CT FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol ICC ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) Test Conditions(1) VCC = Max. VIN = 3.4V(3) VCC = Max. Outputs Open MR = VCC One Input Toggling 50% Duty Cycle VCC = Max. Outputs Open fCP= 10MHz 50% Duty Cycle MR = VCC One Bit Toggling at fi = 5MHz 50% Duty Cycle VCC = Max. Outputs Open fCP= 10MHz 50% Duty Cycle MR = VCC Eight Bits Toggling at fi = 2.5MHz 50% Duty Cycle Min. -- VIN = VCC VIN = GND -- Typ.(2) 0.5 0.15 Max. 2.0 0.25 Unit mA mA/ MHz
IC
Total Power Supply Current (6)
VIN = VCC VIN = GND
--
1.5
3.5
mA
VIN = 3.4V VIN = GND
--
2.0
5.5
VIN = VCC VIN = GND
--
3.8
7.3 5)
VIN = 3.4V VIN = GND
--
6.0
16.3 (5)
NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCP/2 + fiNi) ICC = Quiescent Current ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Input Frequency Ni = Number of Inputs at fi All currents are in milliamps and all frequencies are in megahertz.
2568 tbl 06
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IDT54/74FCT273T/AT/CT FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT273T Com'l. Symbol Parameter tPLH Propagation Delay CP to ON tPHL tPHL tSU tH tW tW tREM Propagation Delay MR to ON Set-up Time HIGH or LOW DN to CP Hold Time HIGH or LOW DN to CP CP Pulse Width HIGH or LOW MR Pulse Width LOW Recovery Time MR to CP Condition(1)
CL = 50pF RL = 500
Min.
(2)
IDT54/74FCT273AT Com'l.
(2)
IDT54/74FCT273CT Com'l.
(2)
Mil.
(2)
Mil.
(2)
Mil.
(2)
Max. Min.
Max. Min.
Max. Min.
Max. Min.
Max. Min.
Max.
Unit ns ns ns ns ns ns ns
2.0 13.0 2.0 13.0 3.0 2.0 7.0 7.0 4.0 -- -- -- -- --
2.0 15.0 2.0 15.0 3.5 2.0 7.0 7.0 5.0 -- -- -- -- --
2.0 2.0 2.0 1.5 6.0 6.0 2.0
7.2 7.2 -- -- -- -- --
2.0 2.0 2.0 1.5 6.0 6.0 2.5
8.3 8.3 -- -- -- -- --
2.0 2.0 2.0 1.5 6.0 6.0 2.0
5.8 6.1 -- -- -- -- --
2.0 2.0 2.0 1.5 6.0 6.0 2.5
6.5 6.8 -- -- -- -- --
NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays.
2568 tbl 07
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IDT54/74FCT273T/AT/CT FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS
VCC 500 VIN Pulse Generator RT D.U.T. 50pF CL
2568 drw 04
SWITCH POSITION
Test
7.0V
Switch
Open Drain Disable Low Enable Low All Other Tests
Closed
VOUT
Open
500
2568 lnk 08 DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tSU
tH
3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V
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LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
1.5V
tREM
1.5V
2568 drw 06
tSU
tH
PROPAGATION DELAY
3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V
2568 drw 07
ENABLE AND DISABLE TIMES
ENABLE DISABLE 3V CONTROL INPUT tPZL OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH SWITCH CLOSED tPZH SWITCH OPEN 1.5V 0V 0V
2568 drw 08
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
1.5V tPLZ 3.5V 1.5V tPHZ 0.3V VOH 0V 3.5V 0.3V VOL
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control DisableHIGH 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns
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IDT54/74FCT273T/AT/CT FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDTXX Temp. Range FCT X Family XXXX Device Type X Package X Process Blank B P D SO L E Q 273T 273AT 273CT Blank 54 74 Commercial MIL-STD-883, Class B Plastic DIP CERDIP Small Outline IC Leadless Chip Carrier CERPACK Quarter-size Small Outline Package Octal D Flip-Flop w/Clear
High Drive -55C to +125C 0C to +70C
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